1. Field of the Invention
The present invention relates to a semiconductor device having an element isolation region by a trench element isolation structure out of methods of defining the element formation region in a semiconductor substrate, and a method of manufacturing the same.
2. Description of the Prior Art
A known example of structures for electrically isolating elements on a semiconductor substrate is a trench element isolation structure. In this element isolation structure, an insulating film made of, e.g., an oxide film is buried in a trench formed in, e.g., a silicon semiconductor substrate to define an element active region.
In this trench element isolation structure, an electric field tends to concentrate at the end of an element isolation region, resulting in a low threshold voltage of the MOS transistor.
To solve this problem, Japanese Patent Laid-Open Nos. 63-305527 and 1-107554 have disclosed structures in which concentration of electric fields at the end of the element isolation region is relaxed by tapering the upper portion of the trench side wall and vertically forming its lower portion in a trench element isolation structure.
Japanese Patent Laid-Open No. 6-177239 has disclosed a structure in which the entire side wall of a trench is tapered from the top to the bottom in a trench element isolation structure.
Japanese Patent Laid-Open No. 7-161808 has disclosed a method of increasing the angle of the side wall of a trench at its upper end by wet etching.
In the method disclosed in Japanese Patent Laid-Open No. 63-305527, an insulating film is buried in a trench formed in a semiconductor substrate so as not to reach the surface of the semiconductor substrate, and then the edge defined by the trench side wall and semiconductor substrate surface is anisotropically etched away to taper the upper end of the trench side wall.
In the method disclosed in Japanese Patent Laid-Open No. 1-107554, an oxide film is formed on a semiconductor substrate and processed into a mask shape used to form a trench, and then isotropic plasma etching is performed before forming a trench. The upper end of the side wall of a prospective trench is tapered in advance, and anisotropic etching is performed to form a trench, thereby completing a trench having a tapered upper end.
In the method disclosed in Japanese Patent Laid-Open No. 6-177239, dry etching is performed using a cap oxide film as a mask with nitrogen gas and oxygen gas to form a trench having an entirely tapered side wall.
In the method disclosed in Japanese Patent Laid-Open No. 63-305527, however, since the etching process window is narrow, and the edge defined by the trench side wall and semiconductor substrate surface is rounded by wet etching, a tapered surface formed from a uniform inclined surface is difficult to form.
In the method disclosed in Japanese Patent Laid-Open No. 1-107554, since the upper end is tapered by isotropic plasma etching, no inclined surface can be formed. Further, the trench is directly deepened by anisotropic etching after tapering, so the tapered shape may change upon this anisotropic etching.
In the methods disclosed in Japanese Patent Laid-Open Nos. 63-305527 and 1-107554, an oxide film must be directly formed on the semiconductor substrate to fill the trench after tapering, and etched back while being left in the trench. However, no stopper film effective for etch-back is formed.
The oxide film filling the trench, therefore, becomes flush with the semiconductor substrate surface upon etch-back. When a gate wiring layer or interconnect for a MOS transistor is formed on the oxide film filling the trench, the distance between the gate wiring layer and the semiconductor substrate is short. Accordingly, even if the upper portion of the trench is tapered, an electric field concentrates at this portion.
In the method disclosed in Japanese Patent Laid-Open No. 7-161808, since the upper end of the trench is shaped into an inclined surface by wet etching, the trench width unnecessarily widens, resulting in a large element isolation area. This obstructs micropatterning of semiconductor devices and damages the semiconductor substrate exposed in the trench.
As described above, since the taper angle of the trench upper end cannot be uniformly controlled, and the element isolation region is even with the semiconductor substrate surface, concentration of an electric field at the end of the element isolation region cannot be effectively relaxed.
When, therefore, a MOS transistor is formed using the trench element isolation structure in the prior art, the threshold voltage undesirably varies and decreases.
In the method disclosed in Japanese Patent Laid-Open No. 6-177239, since the entire side wall of the trench is tapered, no trench except for a trench having a constant aspect ratio can be formed. In other words, the trench depth is naturally determined by the trench width. To ensure satisfactory element isolation performance, the element isolation region must be made wide, which obstructs micropatterning of elements. In addition, in the trench element isolation structure, when a multilayered film serving as a trench formation mask is removed or when cleaning is performed later, the end of the insulating film filling the trench is removed to recess it from the semiconductor substrate surface.
If the gate electrode of a MOS transistor is formed over the recess, an electric field concentrates at the boundary between the insulating film and the semiconductor substrate, i.e., the element isolation end of the trench element isolation structure, resulting in a low threshold voltage and a large leakage current of the transistor.
Methods for solving this problem are disclosed in Japanese Patent Laid-Open Nos. 6-21210 and 7-273180.
According to these references, a multilayered film serving as a trench formation mask is formed on a semiconductor substrate, a trench formation portion is selectively removed to form an opening, and then a silicon oxide film is formed by CVD on the entire surface of the semiconductor substrate to temporarily fill the opening.
The silicon oxide film is removed from the multilayered film by anisotropic etching to form a side wall made of the silicon oxide film on the side wall of the multilayered film in the opening. In forming a trench in the semiconductor substrate, etching is performed using the side wall and the multilayered film as a mask.
After forming the trench, a silicon oxide film is formed by CVD to fill the trench, the silicon oxide film is removed from the multilayered film, and then the multilayered film used as a mask is removed to complete the trench element isolation structure.
According to these methods, since the opening is narrowed by the side wall on the multilayered structure, the side wall made of the silicon oxide film is left at the side edge of the silicon oxide film buried in the trench upon removing the multilayered film. Therefore, the trench element isolation structure is wider than the trench width by the side wall thickness in the semiconductor substrate.
In removing the multilayered film or in subsequent cleaning, the side wall is removed before the silicon oxide film filling the trench is removed. Accordingly, the side wall serves as a protective film to prevent formation of the above-described recess at the element isolation end.
However, even if the side wall is formed of the silicon oxide film to widen the trench element isolation structure, as described above, the silicon oxide film forming the side wall does not satisfactorily function as a protective film against etching or cleaning.
More specifically, in the above methods, the silicon oxide film formed by CVD is used as a sidewall. Hot phosphoric acid is employed in order to remove a silicon nitride film generally used as a trench formation mask film, but the silicon oxide film formed by CVD cannot attain a sufficiently high etching selectivity with respect to the silicon nitride film.
Similarly, the side wall made of the silicon oxide film cannot sufficiently protect the silicon oxide film filling the trench from subsequent cleaning.
In, therefore, removing the silicon nitride film with hot phosphoric acid, or performing etching or cleaning later, the side wall is entirely removed to form a recess at the boundary between the silicon oxide film filling the trench and the semiconductor substrate.
When the gate electrode of a MOS transistor is formed over the recess, an electric field concentrates at the element isolation end of the trench element isolation structure, resulting in a low threshold voltage and a large leakage current of the transistor.
The present invention solves this problem, and provides a semiconductor device having a trench element isolation structure having good electrical characteristics and high reliability by relaxing concentration of an electric field at an element isolation end, and a method of manufacturing the same.
A semiconductor device according to the present invention comprises a trench formed in a semiconductor substrate, and an insulating film filling the trench, the trench having a side wall constituted by an upper inclined surface making a predetermined angle with a surface of the semiconductor substrate, and a lower surface substantially perpendicular to the surface of the semiconductor substrate, and having a flat bottom surface.
Another aspect of the semiconductor device according to the present invention comprises a trench element isolation structure formed by an insulating film filling a trench in a semiconductor substrate, the insulating film projecting from a surface of the semiconductor substrate, and having a side edge on the semiconductor substrate which is covered with a thermal oxide film formed by thermally oxidizing a polysilicon film.
A method of manufacturing a semiconductor device according to the present invention comprises the first step of forming a first insulating film on a semiconductor substrate, the second step of selectively removing the first insulating film to partially expose the semiconductor substrate, the third step of removing the semiconductor substrate exposed conforming to a shape of the first insulating film, thereby forming a first trench having a side wall formed by an inclined surface making a predetermined angle with a surface of the semiconductor substrate, the fourth step of forming a second insulating film to cover an inner wall surface of the first trench including the inclined surface, the fifth step of removing the second insulating film from a bottom surface of the first trench to expose the semiconductor substrate on the bottom surface of the first trench, the sixth step of removing the semiconductor substrate exposed on the bottom surface of the first trench, thereby forming a second trench which continues from a side wall of the first trench and has a side wall substantially perpendicular to the surface of the semiconductor substrate, the seventh step of forming a third insulating film on an entire surface including inner surfaces of the first and second trenches, thereby filling the first and second trenches, the eighth step of removing the third insulating film until the first insulating film is exposed, and the ninth step of removing the first insulating film.
Another aspect of the method of manufacturing a semiconductor device according to the present invention comprises the first step of forming a first insulating film on a semiconductor substrate, the second step of forming a second insulating film on the first insulating film, the third step of selectively removing the second insulating film to form an opening through which the first insulating film is exposed, the fourth step of forming an oxidizable film on an entire surface of the semiconductor substrate, the fifth step of removing the oxidizable film until the first insulating film is exposed in the opening, thereby forming a first side wall made of the oxidizable film at a side wall of the second insulating film in the opening, the sixth step of forming a third insulating film on the entire surface of the semiconductor substrate, the seventh step of removing the third insulating film until the semiconductor substrate is exposed in the opening, thereby forming a second side wall made of the third insulating film so as to cover the first side wall, the eighth step of removing the semiconductor substrate exposed in the opening by using the second insulating film and the second side wall as a mask, thereby forming a trench in the semiconductor substrate, the ninth step of forming a fourth insulating film on the entire surface of the semiconductor substrate to fill the trench, the 10th step of removing the fourth insulating film until the second insulating film is exposed, the 11th step of removing the first and second insulating films to expose the underlying semiconductor substrate, and the 12th step of heat-treating the semiconductor substrate to thermally oxidize the first side wall made of the oxidizable film.
Still another aspect of the method of manufacturing a semiconductor device according to the present invention comprises the first step of forming a first insulating film on a semiconductor substrate, the second step of selectively removing the first insulating film to form an opening through which the semiconductor substrate is exposed, the third step of forming an oxidizable film on an entire surface of the semiconductor substrate, the fourth step of heat-treating the semiconductor substrate to form a thermal oxide film of the oxidizable film, the fifth step of removing the thermal oxide film on the first insulating film to form a side wall made of the thermal oxide film at a side wall of the first insulating film in the opening, the sixth step of removing the semiconductor substrate exposed in the opening by using the first insulating film and the side wall as a mask, thereby forming a trench in the semiconductor substrate, the seventh step of forming a second insulating film on an entire surface of the semiconductor substrate to fill the trench, the eighth step of removing the second insulating film until the first insulating film is exposed, and the ninth step of removing the first insulating film to expose the underlying semiconductor substrate.
Still another aspect of the method of manufacturing a semiconductor device according to the present invention comprises the first step of forming a first insulating film on a semiconductor substrate, the second step of forming a second insulating film on the first insulating film, the third step of selectively removing the second insulating film to form an opening through which the first insulating film is exposed, the fourth step of forming an oxidizable film on an entire surface of the semiconductor substrate, the fifth step of removing the oxidizable film until the first insulating film is exposed in the opening, thereby forming a first side wall made of the oxidizable film at a side wall of the second insulating film in the opening, the sixth step of forming a third insulating film on the entire surface of the semiconductor substrate, the seventh step of removing the third insulating film and the first insulating film until the semiconductor substrate is exposed in the opening, thereby forming a second side wall made of the third insulating film so as to cover the first side wall, the eighth step of removing the semiconductor substrate exposed in the opening by using the second insulating film and the second side wall as a mask, thereby forming a first trench having a side wall formed by an inclined surface making a predetermined angle with the surface of the semiconductor substrate, the ninth step of forming a fourth insulating film on an inner wall surface of the first trench including the inclined surface, the 10th step of removing the fourth insulating film from a bottom surface of the first trench, thereby exposing the semiconductor substrate on the bottom surface of the first trench, the 11th step of removing the semiconductor substrate exposed on the bottom surface of the first trench, thereby forming a second trench which continues from a side wall of the first trench and has a side wall substantially perpendicular to the surface of the semiconductor substrate, the 12th step of forming a fifth insulating film on an entire surface including inner surfaces of the first and second trenches, thereby filling the first and second trenches, the 13th step of removing the fifth insulating film until the second insulating film is exposed, the 14th step of removing the first and second insulating films to expose the underlying semiconductor substrate, and the 15th step of heat-treating the semiconductor substrate to thermally oxidize the first side wall made of the oxidizable film.
Still another aspect of the method of manufacturing a semiconductor device according to the present invention comprises the first step of forming a first insulating film on a semiconductor substrate, the second step of selectively removing the first insulating film to form an opening through which the semiconductor substrate is exposed, the third step of forming an oxidizable film on an entire surface of the semiconductor substrate, the fourth step of heat-treating the semiconductor substrate to form a thermal oxide film of the oxidizable film, the fifth step of removing the thermal oxide film until the surface of the semiconductor substrate is exposed in the opening, thereby forming a side wall made of the thermal oxide film at side walls of the first and second insulating films in the opening, the sixth step of removing the semiconductor substrate exposed in the opening by using the first insulating film and the side wall as a mask, thereby forming a first trench having a side wall formed by an inclined surface making a predetermined angle with the surface of the semiconductor substrate, the seventh step of forming a second insulating film on an inner wall surface of the first trench including the inclined surface, the eighth step of removing the second insulating film from a bottom surface of the first trench to expose the semiconductor substrate on the bottom surface of the first trench, the ninth step of removing the semiconductor substrate exposed on the bottom surface of the first trench, thereby forming a second trench which continues from a side wall of the first trench and has a side wall substantially perpendicular to semiconductor substrate surface, the 10th step of forming a third insulating film on an entire surface including inner surfaces of the first and second trenches, thereby filling the first and second trenches, the 11th step of removing the third insulating film until the first insulating film is exposed, and the 12th step of removing the first insulating film.
In the present invention, after a first trench having a side wall formed by a uniformly inclined surface is formed in a semiconductor substrate, etching is performed while only this inclined surface is covered with a second insulating film, thereby removing the semiconductor substrate exposed on the bottom surface and forming a second trench. Accordingly, a trench whose upper half portion is constructed by the uniformly inclined surface making a predetermined angle with semiconductor substrate surface, and lower half portion is constructed by the substantially vertical side wall can be formed with high controllability.
If dry etching is performed in preferably a chlorine atmosphere or an atmosphere mixture of hydrogen bromide and chlorine in forming the first trench, the side wall of the first trench can stably form an inclined surface. When dry etching is performed in an atmosphere mixture of hydrogen bromide and oxygen in forming the second trench, the side wall of the second trench can be formed into a surface almost perpendicular to semiconductor substrate surface.
In this manner, by forming a uniformly inclined surface at the upper end of the trench side wall, the inclined surface formed with high controllability can disperse even an electric field generated at the end of the element isolation region and can relax concentration of an electric field.
Since the lower half portion of the trench side wall is formed perpendicular to semiconductor substrate surface, the trench can be made sufficiently deep. Therefore, elements can be reliably isolated.
Further, in the present invention, in forming a trench element isolation structure, a trench is formed in the semiconductor substrate using, as a mask, a mask film having an opening and a second side wall covering an oxidizable film (first side wall) formed on the side wall of the opening. The trench is filled with an insulating film, and then the mask film is removed. As a result, the oxidizable film can be left via the second side wall at the side edge of the insulating film filling the trench on the semiconductor substrate. By thermally oxidizing the oxidizable film, the side edge of the insulating film filling the trench can be covered with and protected by the thermal oxide film.
In the present invention, in forming a trench element isolation structure, a trench is formed in the semiconductor substrate using, as a mask, a mask film having an opening and a side wall made of a thermal oxide film formed in the opening. The trench is filled with an insulating film, and then the mask film is removed. With this processing, the side edge of the insulating film filling the trench can be covered with and protected by the thermal oxide film on the semiconductor substrate.
In this case, the oxidizable film is preferably a polysilicon film. A thermal oxide film formed by thermally oxidizing the polysilicon film has an etching rate ⅙ smaller than that of a silicon oxide film formed by CVD method, so is hardly removed by etching, cleaning, and the like. In removing the mask film or performing subsequent etching or cleaning, the thermal oxide film functions as a protective film to prevent the insulating film in the trench from being removed.
According to the present invention, in a semiconductor device having a trench element isolation structure, concentration of an electric field at an element isolation end can be relaxed. Therefore, a semiconductor device having good electrical characteristics and high reliability, and a method of manufacturing the same can be provided.